BUSIRQCLR=0, BUSIRQEN=0, ENUMIRQCLR=0, DLISTIRQEN=0, DLISTIRQCLR=0, ENUMIRQEN=0
Interrupt Control Register
| ENUMIRQEN | ENUMIRQ interrupt mask enable 0 (0): disable (mask) ENUMIRQ 1 (1): enable (unmask) ENUMIRQ |
| DLISTIRQEN | DLISTIRQ interrupt mask enable 0 (0): disable (mask) DLISTIRQ 1 (1): enable (unmask) DLISTIRQ |
| ENUMIRQCLR | Clear enumeration interrupt ENUMIRQ 0 (0): no ENUMIRQCLR clear 1 (1): clear ENUMIRQCLR |
| DLISTIRQCLR | Clear display list interrupt DLISTIRQ 0 (0): no DLISTRQCLR clear 1 (1): clear DLISTRQCLR |
| BUSIRQEN | BUSIRQ interrupt mask enable 0 (0): disable (mask) BUSIRQ 1 (1): enable (unmask) BUSIRQ |
| BUSIRQCLR | Clear bus error interrupt BUSIRQ 0 (0): no BUSIRQCLR clear 1 (1): clear BUSIRQCLR |